The following patents/patent applications are hereby incorporated herein by reference:
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a ferroelectric memory device.
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied thereto is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (xe2x80x9cEEPPROMxe2x80x9d) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for an FeRAM. The memory size and memory architecture affects the read and write access times of an FeRAM. Table 1 illustrates exemplary differences between different memory types.
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. An FeRAM cell may be selected by two concurrent X and Y voltage pulses, respectively, wherein X and Y correspond to a specific bit line and word line, respectively, identified by horizontal and vertical decoder circuitry. The FeRAM cells of the capacitor array which receive only one voltage pulse remain unselected while the cell that receives both an X and Y voltage signal flips to its opposite polarization state or remains unchanged, depending upon its initial polarization state, for example.
Two types of ferroelectric memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T/1C cell 10 is read from by applying a signal to the gate 16 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL) 20. The potential on the bitline 18 of the transistor 12 is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline 18 and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art FIG. 2, a 2T/2C memory cell 30 in a memory array couples to a bit line (xe2x80x9cbitlinexe2x80x9d) 32 and an inverse of the bit line (xe2x80x9cbitline-barxe2x80x9d) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and 42, respectively. The first transistor 36 couples between the bitline 32 and a first capacitor 40, and the second transistor 38 couples between the bitline-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the drive line DL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the dual capacitor ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bitline 32 and the barxe2x80x94bar line 34 corresponding to a logic state to be stored in memory. The common terminal 44 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the dual capacitor memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bar 32 and the barxe2x80x94bar line 34, respectively. A differential signal (not shown) is thus generated across the bitline 32 and the barxe2x80x94bar line 34 by the dual capacitor memory cell 30. The differential signal is sensed by a sense amplifier (not shown) which provides a signal corresponding to the logic level stored in memory.
A memory cell of a ferroelectric memory is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to the fabrication of an FeRAM device that is either a stand-alone device or one which is integrated onto a semiconductor chip that includes many other device types. Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and backend processing techniques used for fabricating the various logic and analog devices on the chip to fabricate this chip which will include FeRAM devices. In other words, it is beneficial to utilize as much of the process flow for fabricating these standard logic devices (in addition to I/O devices and potentially analog devices) as possible, so as not to greatly disturb the process flow (thus increase the process cost and complexity) merely to integrate the FeRAM devices onto the chip.
The following discussion is based on the concept of creating the ferroelectric capacitors in an FeRAM process module that occurs between the front end module (defined to end with the formation of tungsten, which has the chemical symbol W, contacts) and backend process module (mostly metallization). Other locations of the FeRAM process module have also been proposed. For example, if the FeRAM process module is placed over the first layer of metallization (Metal-1) then a capacitor over bitline structure can be created with the advantage that a larger capacitor can be created.
Another possible location for the FeRAM process module is near the end of the back-end process flow. One advantage of this approach is that it keeps new contaminants in the FeRAM module (Pb, Bi, Zr, Ir, Ru, or Pt) out of more production tools. This solution is most practical if the equipment used after deposition of the first FeRAM film is dedicated to the fabrication of the FeRAM device structures and, therefore, is not shared. However, this solution may have the drawback of requiring FeRAM process temperatures compatible with standard metallization structures (suggested limitations discussed above). In addition, the interconnection of the FeRAM capacitor to underlying transistors and other needs of metallization may not be compatible with a minimum FeRAM cell size.
The requirements for the other locations will have many of the same concerns but some requirements may be different.
The FeRAM process module is preferably compatible with standard logic and analog device front-end process flows that include, for example, the use of tungsten contacts as the bottom contact of the capacitor. The FeRAM thermal budget is preferably low enough so that it does not impact substantially the front end structures such as the low resistance structures (which includes the tungsten plugs and silicided source/drains and gates) employed in many logic devices. In addition, transistors and other front end devices, such as diodes, may be sensitive to contamination. Contamination from the FeRAM process module, either direct (such as by diffusion in the chip) or indirect (cross contamination through shared equipment), should be addressed so as to avoid transistor and diode degradation. The FeRAM devices and process module should also be compatible with standard backend process flow. Therefore the FeRAM process module should have minimum degradation of logic metallization""s resistance and parasitic capacitance between metal and transistor. In addition, the FeRAM devices should not be degraded by the backend process flow with minimal, if any modification. This is a significant challenge since ferroelectric capacitors have been shown to be sensitive to hydrogen degradation and most logic backend process flows utilize hydrogen and/or deuterium in many of the processes (such as in the formation of SiO2 and Si3N4, CVD tungsten deposition, SiO2 via etch, and forming gas anneals).
Commercial success of FeRAM also advantageously addresses minimization of embedded memory cost. Total memory cost is primarily dependent on cell size, periphery ratio size, impact of yield, and additional process costs associated with memory. In order to have cost advantage per bit compared to standard embedded memories such as embedded DRAM and Flash it is desirable to have FeRAM cell sizes that are similar to those obtained with standard embedded memory technology. Some of the methods discussed in this patent to minimize cell size include making the process flow less sensitive to lithography misalignment, forming the capacitor directly over the contact, and using a single mask for the capacitor stack etch. Some of the methods discussed in this patent, to reduce the added process cost, may require two additional masks for the FeRAM process module and a planar capacitor which reduces the complexity of the needed processes.
Although this patent focuses on using a planar capacitor, a three dimensional capacitor using post or cup structure can be fabricated using many of the same concepts and processes. The planar structure is illustrated because it uses a simpler process and is cheaper to make. The 3D capacitor is preferred when the planar capacitor area needed for minimum charge storage considerations limits the cell size. In this situation, the capacitor area enhancement associated with the 3D configuration allows a smaller planar cell size. DRAM devices have used this approach for many years in order to reduce cell area.
The present invention relates to a method of forming an FeRAM capacitor, wherein an etch associated with a bottom electrode layer does not adversely impact FeRAM capacitor integrity or performance. The present invention employs the addition of a protective layer or film on a sidewall of the capacitor stack after the patterning of the top electrode layer and the ferroelectric dielectric layer, but prior to the patterning of the bottom electrode layer. Subsequently, when the bottom electrode layer is patterned via, for example, an etch process, the sidewalls of the capacitor stack are protected from contamination associated with the bottom electrode layer. The protective sidewall layer thus prevents a shorting out of the capacitor or a leakage associated therewith due to conductive contaminants associated with the bottom electrode layer.
According to one exemplary aspect of the present invention, a method of forming an FeRAM capacitor is disclosed. The method comprises forming a bottom diffusion barrier layer over a substrate, and forming a bottom electrode layer, a ferroelectric dielectric layer and a top electrode layer thereon. The top electrode layer and the ferroelectric layer are then patterned to define a capacitor stack structure having sidewalls associated therewith. The method further comprises forming a protection layer over the capacitor stack structure, thereby covering an exposed portion of the bottom electrode layer as well as a top portion and the sidewalls of the capacitor stack structure.
The protection layer is then patterned, for example, by etching with a substantially anisotropic etch, thereby removing the material on the exposed portion of the bottom electrode layer as well as the top portion of the capacitor stack structure, and leaving a portion on the sidewalls of the capacitor stack structure. Subsequently, the bottom electrode layer is patterned. During such patterning, the protection layer on the sidewall of the capacitor stack structure protects the ferroelectric dielectric layer from contamination associated with the bottom electrode layer, thus preventing capacitor degradation, for example, due to leakage.
According to another aspect of the present invention, the protection layer comprises an AlOx film having a thickness sufficient to protect the sidewalls of the capacitor stack structure during the subsequent patterning of the bottom electrode layer. Such thickness may be a function of several factors; for example, the film thickness may depend upon the aspect ratio of the capacitor stack structure, the manner of forming the protection layer, step coverage of the protection layer, subsequent etch chemistry, etc. In accordance with one exemplary aspect of the invention, the sidewall thickness of the AlOx film is about 80 Angstroms or more and about 200 Angstroms or less.
According to yet another aspect of the present invention, the AlOx protection layer is formed over the capacitor stack structure via metal organic chemical vapor deposition using aluminum precursors. Alternatively, the protection layer may be formed via reactive sputtering. In addition, in one exemplary aspect, the AlOx protection layer is patterned using an etch that is selective with respect to the top electrode layer and the bottom electrode layer, respectively. For example, the AlOx protection may be etched using a dry etch with a Cl2 and O2 etch chemistry with a fluorine containing gas such as CF4, CxFy or CxHyFz.
According to still another aspect of the present invention, the protection layer may comprise a multi-layer film such as an AlOx and an AlN film. For example, the multi-layer film may comprise an AlOx film followed by an AlN film formed thereover. In accordance with one example, the thickness of the AlN on the sidewall of the capacitor stack structure is about 400 Angstroms, and the AlOx and AlN films are formed via physical vapor deposition.
In the case of a multi-layer protection layer formed over the capacitor stack structure, the patterning of the protection layer may comprise a multi-step dry etch process, wherein the AlN film is first etched with a Cl2 chemistry, and the AlOx film is subsequently etched with a Cl2 and O2 chemistry with a fluorine containing gas. In the above manner, the multi-layer protection layer is patterned in a substantially anisotropic manner, thereby removing portions associated with an exposed portion of the bottom electrode layer (not covered by the capacitor stack) and a top portion of the capacitor stack structure, while leaving a portion on the capacitor stack structure sidewalls for protection of the capacitor during a subsequent patterning of the bottom electrode layer.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.